Connections are valid for TTL TX to RX and RX to TX

Note: https://templates.blakadder.com/great_value_wiz_6000201696362.html these have been updated to ESP32-C3 with SecureBoot enabled. I saw this URL and bought it then found out it is now different :(

“A fatal error occurred: WARNING: Detected flash encryption enabled and download manual encrypt disabled. Flashing plaintext binary may brick your device! Use –force to override the warning.”

This is a 2AGBW-WIZ2012 which is a ESP32-C3. It has the SecureBoot efuses set so if you try to /force flash it without the keyfile you will brick it into a boot loop. https://github.com/espressif/esptool/issues/699

https://fcc.report/FCC-ID/2AGBW-WIZ2012

https://usermanual.wiki/m/21b6fd4f6a7c28eaaffbd9b8f07fb65655032fc7896754a2948c302beb656d06_optim.pdf

Espressif Systems 9 ESP32-C3-WIZ2012 Datasheet v0.6

Pin Description

The module has 8 pins and 6 test points. Please find details in Table 2 and Table 3. For peripheral pin configurations, please refer to ESP32-C3 Family Datasheet . By default, most GPIOs of the ESP32-C3FH4 chip do not have internal pull-up or pull-down resistors. You can add them yourself.

Table 2: Pin Definitions

Name No. IO No. Function

IRR 1 IO18 GPIO or IRR GND 2 — Ground CW 3 IO10 PWM output VDD 4 — 3.3 V power input WW 5 IO7 PWM output R 6 IO6 PWM output G 7 IO4 PWM output B 8 IO5 PWM output

Table 3: Test Point Definitions

Name IO No. Function

GND — Ground RX IO20 Debug UART data reception TX IO21 Debug UART data transmission VDD — 3.3 V power input EN — Module enable signal (internal pull-up by default). Active high BOOT IO9 0: Download boot mode; 1: SPI boot mode (default) “